In digital electronic circuits, it is often desirable to provide a way for selectively controlling the polarity of a signal. A circuit designer may, for example, wish to design a circuit where the polarity of a clock signal can be changed in response to a select signal. In programmable logic circuits, such as Field Programmable Gate Arrays or Programmable Logic Devices, it is often desirable to allow the end user to configure the polarity of a signal by setting a RAM bit. Such programmability is generally accomplished by a "selective inverter," which is an inverter circuit that in response to a select signal either provides at its output the inverse of its input or its non-inverted input. A selective inverter circuit is also referred to in the art as a "polarity control circuit".
FIG. 1 shows one type of polarity control circuit useable in CMOS integrated circuit designs. As shown in FIG. 1, the input signal, after passing through inverters 10 and 13, and its complement, from inverter 10, are input into a 2:1 multiplexer made up of CMOS transmission gates 20 and 23. The signal SELECT and its complement, from the output of inverter 16, turn on either transmission gate 20 or 23. When SELECT is high, gate 23 is on, gate 20 is off, and the OUTPUT signal follows the INPUT signal. When SELECT is low, gate 20 is on, gate 23 is off, and the OUTPUT signal is the inverse of the INPUT signal.
The 2:1 multiplexer implementation shown in FIG. 1 has two notable disadvantages. First, the output signal is being driven through a transmission gate, either 20 or 23, which is undesirable in terms of speed and for driving large capacitive loads. An additional buffer stage can be added following the transmission gate but this will add a further delay. Secondly, an inherent skew is introduced between the two polarities due to the presence of one additional inverter 13 in the true data path.
FIG. 2 shows a polarity control circuit designed to correct some of these deficiencies. As shown in FIG. 2, the input signal is passed through a modified inverter constructed from transistors 30 and 33. The invertor is modified by driving the sources of transistors 30 and 33 with complementary SELECT logic functions rather than hard wiring each to its respective power rail as would be done in a typical inverter.
The circuit of FIG. 2 will have improved driving characteristics because the output node is driven directly by a power stage, inverter 36. The circuit of FIG. 2 will additionally have less skew between polarities because there is only one path for signal flow from input to output.
However, one limitation of this circuit is that the intermediate node HO does not swing to full CMOS levels when the SELECT signal is low, and hence DC power is consumed in the second stage because one of the two transistors forming inverter 36 is not completely turned off. This is clearly undesirable for low voltage applications or in designs that require minimum standby current consumption. Programmable Logic Device designs often require minimum standby current consumption and may incorporate a large number of polarity control circuits thereby compounding the problem.
What is needed is a polarity control circuit with fast speed and good driving characteristics that consumes essentially zero standby current.